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A short glossary of terms used in the magazine. This will be revised and added to as necessary. Your suggestions for relevant terms to add are welcome.

Damon Hart-Davis, Computing Editor dhd@exnet.com.

Byte Sex
This is the order in which bits are numbered in a byte; the highest-numbered bit the most significant (the usual case, eg in the Intel x86 family, the SPARC, 68xxx, etc), or vice versa (as in some of the Texas Instruments chips such as the 9900). More-or-less irrelevant except to the most spoddy and to compiler and hardware designers.
CISC (Complex Instruction-Set Computer)
A processor design style which attempts to provide direct support for high-level language compilers with `complex' instructions, but tends to slow down the bread-and-butter processing more that it is worth; cf RISC and VLIW. The Intel x86 and Motorola 68000 ranges are examples of CISC.
IP (Internet Protocol) `new generation', more formally known as IP version 6 (IPv6), the networking protocol that looks set to surplant the current IP version 4 protocol as the basic lanaguage of the Internet itself at the turn of the century. See the IETF's working papers on IPng.
A style of programming that allows many separate threads of control inside one process, eg within one UNIX `heavy-weight' process. Multithreading is often used to minimise overhead when a number of closely-cooperating, concurrently-executing, program fragments do not need the full weight of normal inter-process protection from the OS, and indeed where the overhead of providing such protection is prohibitive. Network-based information servers are often candidates for multi-threading where the individual operations are short, most operations are I/O bound, and a large number of logical copies of the server are operational at once; NFS and HTTPD (Web) servers are good candidates for multithreading for example.

See editorial 96/01/15; Solaris Multithreaded Programming Guide ISBN 0-13-160896-7; a multithreaded Web query server; the announcement of the IEEE POSIX pthreads multithreading standard; Sun's threads FAQ.

VLIW (Very Long Instruction Word)
Can be seen as an extension of the RISC principle; less emphasis on formal `instructions' such as ``add register 8 to register 9 and store in register 1'' and more on opening connections between functional units on the CPU. The compiler has to work very hard and intimately understand the CPU, but in return can achieve very high levels of parallelism and performance from the silicon. Portability of code is probably compromised in return for this, viewed naively; cf CISC and RISC.

Some further reading:
See editorial 95/12/18; Intel/HP collaboration and the P7; a bibliography; BYTE article; the JIFFE Robot Control Processor; the M-Machine successor to the Multiflow Trace; the MOVE project at University of Delft, Holland; ``Percolation Scheduling is a system for performing parallelizing transformations for the VLIW and superscalar computation models,'' Philips TriMedia division's VLIW DSP; Lycos search for VLIW.

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Last updated 96/12/10.